Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Andrew E. Horch0
Date of Patent
July 19, 2011
0Patent Application Number
124104170
Date Filed
March 24, 2009
0Patent Primary Examiner
Patent abstract
A Non-Volatile Memory (NVM) cell and programming method in which the cell can denote at least two logic levels (e.g., 0 and 1) and includes a read-transistor with a floating gate and a Band-To-Band-Tunneling device (BTBT device) sharing the floating gate with the read-transistor. The BTBT device is configured as an injection device for injecting a first charge onto the floating gate when the BTBT device is biased so that it is in accumulation, to set at least one of the logic levels.
Timeline
No Timeline data yet.
Further Resources
No Further Resources data yet.