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US Patent 7972950 Method of fabricating semiconductor device having dual gate

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Patent abstractTimelineTable: Further ResourcesReferences
Is a
Patent
Patent
1

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
1
Patent Number
79729501
Patent Inventor Names
Hag-ju Cho1
Sang-jin Hyun1
Sug-hun Hong1
Yu-gyun Shin1
Hong-bae Park1
Hoon-joo Na1
Hyung-seok Hong1
Date of Patent
July 5, 2011
1
Patent Application Number
125803021
Date Filed
October 16, 2009
1
Patent Citations Received
‌
US Patent 11764279 Semiconductor device and method for manufacturing the same
Patent Primary Examiner
‌
Charles D. Garber
1
Patent abstract

A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.

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