US Patent 7957949 Hierarchical system design

Patent 7957949 was granted and assigned to Cadence Design Systems on June, 2011 by the United States Patent and Trademark Office.

Overview Structured Data Issues Contributors Activity

Is a

Patent

Patent attributes

Current Assignee

Cadence Design Systems

Patent Jurisdiction

United States Patent and Trademark Office

Patent Number

79579490

Patent Inventor Names

Pero Subasic0

Enis Aykut Dengi0

Date of Patent

June 7, 2011

Patent Application Number

126856050

Date Filed

January 11, 2010

Patent Primary Examiner

‌

Mary C Jacob

Patent abstract

A method of system design, and more particularly a method of designing systems that achieve a set of performance goals using a hierarchically partitioned system representation wherein performance simulations are performed at multiple levels within the hierarchy and are combined to simulate a system level result in order to reduce the aggregate time required for performance simulation.