Patent attributes
A flat-panel display having simplified test architecture is disclosed for reducing substrate border area. The flat-panel display includes a plurality of data lines, a plurality of gate lines, a plurality of first conductive lines, a plurality of first one-way switching units, a plurality of second one-way switching units, a plurality of control units and a second conductive line. The gate lines are used to deliver gate signals for use in a test. Each first one-way switching unit functions to allow one-way signal transmission from a corresponding first conductive line to a corresponding gate line. Each second one-way switching unit functions to allow one-way signal transmission from a corresponding first conductive line to the second conductive line. The second conductive line is employed to deliver a corresponding gate signal furnished by a corresponding second one-way switching unit. Each control unit controls inputting of test data signals to one corresponding data line.
