Patent attributes
A delay locked loop circuit includes: a voltage level detector for detecting of an external power source voltage level; a phase comparator for comparing phases of reference clock and feedback clock; a clock delayer for designating one of a first delay cell unit and a second delay cell unit as initial delay cell unit and the other as connected delay cell unit, delaying the reference clock by the initial delay cell unit until delay amount of the reference clock reaches a predetermined delay amount, delaying the reference clock by the connected delay cell unit after the delay amount of the reference clock reaches the predetermined delay amount in response to an output signal of the phase comparator, and outputting a delay locked clock; and a delay duplication modeler for changing the delay locked clock to reflect an actual delay condition of the reference clock and outputting the feedback clock.
