US Patent 7948912 Semiconductor integrated circuit with test mode

A semiconductor integrated circuit is provided which includes: A signal input terminals which include control input pads, A being an integer greater than or equal to 2; an internal circuit; a clock signal input terminal to which a clock signal is input; and an input signal control block which, in a test mode, separates time-division multiplexed data having a multiplicity of X, the time-division multiplexed data being input from A/X signal input terminals among the A signal input terminals, into individual data in accordance with the clock signal, and outputs the separated individual data to the internal circuit, X being an integer greater than or equal to 2.