Patent attributes
The present invention relates to a semiconductor memory, and more specifically, to a data output circuit capable of differentiating global data lines in accordance to an operation mode to output them to a data input/output pin. The present invention includes: a multiplexer selecting any one of a plurality of global input/output lines which can receive variable data bandwidth directed by control signals and which can output data carried on the selected global input/output line, and a controller generating the control signals in accordance to operation mode signals corresponding to a data bandwidth and address signals provided for selecting data and providing them to the multiplexer. Thereby, the present invention can realize an improved data read speed by reducing the loading of the global input/output line.
