Patent attributes
Methods, memory devices, and systems are disclosed, such as those for accessing a memory circuit through the use of reduced external pins. With one such system, a single external pin receives a global memory select signal which transmits an access signal for one of a plurality of memory circuits in a system. The memory circuits may be stacked and may also be ranked memory circuits. The global memory select signal may be sent to a counter. Such a counter could count the length of time that the global memory select signal is active, and based on the counting, sends a count signal to a comparator. The comparator may compare the count signal with a programmed value to determine if a specific memory chip and/or port is to be accessed. This configuration may be duplicated over multiple ports on the same memory device, as well as across multiple memory ranks.
