Patent attributes
A FET bias circuit applies a bias voltage that is not adjusted separately to an amplifying element FET of a FET amplifying circuit. In the FET bias circuit is provided a monitor element FET m having a gate connected to the gate of the amplifying element FET a and a source connected to the source of the amplifying element FET a, respectively, and having a drain current with respect to the bias voltage substantially proportional to the drain current of the amplifying element FET a. In the FET bias circuit is further provided a fixed bias circuit for applying the bias voltage so that the amplifying element FET a enters a predetermined operating class by applying a bias voltage to the monitor element FET m so that a drain current flowing to the monitor element FET m enters a predetermined operating class.
