Patent attributes
A semiconductor device includes a chip, a laminated wiring structure formed integrally with the chip, a frame disposed to surround the chip and made of a material having stiffness, and a sealing resin formed to bury therein the frame and at least the periphery of the side surface of the chip. The laminated wiring structure includes a required number of wiring layers, which are formed by patterning in such a manner that a wiring pattern directly routed from an electrode terminal of the chip is electrically connected to pad portions for bonding external connection terminals, the pad portions being provided, at a position directly below a mounting area of the chip and at a position directly below an area outside the mounting area, on a surface to which the external connection terminals are bonded.
