Patent 7943400 was granted and assigned to NetLogic Microsystems on May, 2011 by the United States Patent and Trademark Office.
An semiconductor device having a plurality of fabrication layers. A first region of a first fabrication layer of the semiconductor device is revised. To signal the revision, a connectivity structure in a second region of the first fabrication layer is omitted to interrupt an otherwise continuous signal path that extends through a plurality of interconnection layers of the semiconductor device.