Patent attributes
According to one embodiment, an instruction decoder for a computer processor includes a fixed instruction decoding portion and at least one look up table having a plurality of random access memory elements. The fixed instruction decoding portion has an input for receiving program instructions and an output coupled to a back-end processing engine. The instruction decoder is selectively operable to alternatively decode program instructions associated with a differing instruction set architectures by storage of logical values in the at least one look up table. Decoding of program instructions from one particular instruction set architecture are accomplished using the same logic gates as program instructions form other instruction set architectures.
