US Patent 7940202 Clocking analog components operating in a digital system

In one example, a clock generation component is configured to receive a master clock and generate a plurality of clock signals that are shifted relative to one another for a chip having an analog domain and a digital domain. A first selection component is configured to select a first one of the generated clock signals and drive the digital domain according to the first clock signal. A second selection component is configured to select a second one of the generated clock signals that is shifted relative to the first clock signal currently used to drive the digital domain for driving an analog component of the analog domain.