Patent attributes
A sample-and-hold feed switch has parallel PMOS branches and parallel NMOS branches, each extending from an input node to an output node connected to a hold capacitor. Each PMOS branch has a PMOS switch FET connected to a matching PMOS dummy FET, and each NMOS branch has an NMOS switch FET connected to a matching NMOS dummy FET. A sample clock switches the PMOS switch FETs on and off, and a synchronous inverse sample clock effects complementary on-off switching of the PMOS dummy FETs. Concurrently, a synchronous inverse sample clock switches the NMOS switch FETs on and off, and the sample clock effects a complementary on-off switching of the NMOS dummy FETs. A bias sequencer circuit biases the bodies of the PMOS switch FETs and the bodies of the PMOS dummy FETs, in a complementary manner, and biases the NMOS switch FETs and the NMOS dummy FETs, also in a complementary manner. The on-off switching of the PMOS dummy FETs injects charge, cancelling a charge injection by the PMOS signal switch FETs, and injects glitches cancelling glitches injected by the PMOS signal switch FETs. The on-off switching of the NMOS dummy FETs injects charge that cancels a charge injection by the NMOS signal switch FETs, and injects glitches that cancels glitches injected by the NMOS signal switch FETs.
