US Patent 7928490 Vertical transistor and vertical transistor array

A vertical transistor including a substrate, a gate, a base line and a gate dielectric layer is provided. The substrate includes a pillar protruding out of a surface of the substrate. The pillar includes a first doped region, a channel region and a second doped region from bottom to top. The gate is disposed on a sidewall at one side of the channel region. The base line is disposed on a sidewall at the other side of the channel region and not contacted with the gate. The gate dielectric layer is disposed between the gate and the channel region.