US Patent 7911852 Nonvolatile semiconductor memory device and operation method thereof

A p-type well region is formed at a main surface of a semiconductor substrate. An n-type impurity region is located under the p-type well region. A first insulating layer is formed on the main surface of the semiconductor substrate and on the p-type well region. A charge-storage insulating layer is formed on the first insulating layer. A gate electrode layer is formed on the charge-storage insulating layer. An erase operation is performed by applying a forward bias to the p-type well region and the n-type impurity region to generate hot carriers and inject the hot carriers into the charge-storage insulating layer.