US Patent 7894283 Integrated circuit including selectable address and data multiplexing mode

An integrated circuit includes a memory array, first pads, and second pads. The integrated circuit is configured to operate in a first mode and in a second mode. The first mode includes receiving data signals on the first pads and address signals on the second pads to access the memory array. The second mode includes receiving multiplexed data signals and address signals on the first pads to access the memory array.