US Patent 7890843 Semiconductor memory device

A memory device includes an error detection and correction system with an error correcting code over Galois field GF(2n), which has an operation circuit configured to execute addition/subtraction with modulo 2n−1, wherein the operation circuit includes first and second operation parts for performing addition/subtraction with modulo M and modulo N (where, M and N are integers, which are prime with each other as being obtained by factorizing 2n−1), the first and second operation parts being for performing addition/subtraction simultaneously in parallel with each other to output an operation result of the addition/subtraction with modulo 2n−1, and wherein the first and second operation parts each includes an adder circuit.