Patent attributes
An amplifying device (10) includes first, second, third and fourth transistors (M1, M2, M3, M4). In the first and third transistors (M1, M3) the source is connected to an input signal source (IN+, IN−), the gate is connected to a biasing potential (VB) and the drain is connected to a signal output (O+, O−). There is a first and second branch (B1, B2) between the source and drain of the first and third transistor (M1, M3), respectively, each including a corresponding second or fourth transistor (M2, M4). The device also includes a third branch (B3) comprising a first capacitor (C1) and a first switch (SW1) connected between the first transistor (M1) source and the third transistor (M3) gate, and a fourth branch (B4) comprising a second capacitor (C2) and a second switch (SW2) connected between the third transistor (M3) source and the first transistor (M1) gate.
