Patent attributes
A semiconductor integrated circuit device which substantially reduces drop in a supply voltage generated by a regulator and ensures stable supply of a supply voltage with high efficiency and high accuracy. In the device, a memory power supply includes a plurality of transistors and an error amplifier. In the transistors, source pads and drain pads are alternately arranged in a row along one edge of a semiconductor chip in a peripheral area of the chip. Transistor gates are formed in parallel with the alternately arranged source pads and drain pads (so that the longitudinal direction of the gates is parallel to the direction of the arrangement of the source pads and drain pads). Consequently, the length of wirings coupled to drains and sources is shortened and the sheet resistance is decreased.
