US Patent 7855088 Method for manufacturing integrated circuits by guardbanding die regions

The invention provides a method for manufacturing an integrated circuit. The method, in one embodiment, includes inspecting a semiconductor wafer including a plurality of die for a defect, the inspecting providing an image of the semiconductor wafer including the defect. The method further includes identifying an area of the semiconductor wafer from the image, wherein the identified area encompasses at least those die including any portion of the defect, and dicing the semiconductor wafer into individual die. The die defined by the identified area, in this embodiment, are then discarded.