US Patent 7853752 Caching in multicore and multiprocessor architectures

A multicore processor includes a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; one or more memory interfaces providing memory access paths from the cache memories to a main memory; and one or more input/output modules configured to couple data between an input/output interface and at least one of a memory interface and a cache memory. Each of at least some of the cache memories is assigned as a home location for caching a corresponding portion of the main memory, and is configured to maintain the cache memory based on whether a processor core or an input/output module is requesting access to the cache memory.