Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Date of Patent
November 30, 2010
Patent Application Number
12038042
Date Filed
February 27, 2008
Patent Primary Examiner
Patent abstract
An I/O regulating circuitry is provided. The I/O regulating circuitry omits the ESD device in a CMOS process with a minimized critical dimension to reduce chip size while still maintaining electrostatic discharge immunity. The I/O regulating circuitry is applied in MLC flash memory applications and the flash controller thereof.
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