US Patent 7838941 Electrostatic discharge protection device having a dual triggered transistor

Disclosed is an electrostatic discharge protection device that has a low trigger voltage and protects an internal circuit from electrostatic discharge. The ESD protection device includes an NMOS transistor in which a first pad and a drain are connected to each other and a second pad and a source are connected to each other. A capacitor in which an end is connected to the first pad and the other end is connected to a gate of the NMOS transistor and a substrate contact of the NMOS transistor. The ESD protection devices also includes a resistor in which an end is connected to the second pad and the other end is connected to the capacitor. The first pad may be a power pad and the second pad may be a ground pad. Alternately, the first pad may be an input/output pad and the second pad may be a ground pad.