US Patent 7838389 Enclosed void cavity for low dielectric constant insulator

Field effect devices and ICs (80, 82, 84) with very low gate-drain capacitance Cgd are provided by forming a substantially empty void (70, 100) between the gate (60′) and the drain (27) regions. For vertical FETS a cavity (70, 100) is etched in the semiconductor (SC) (40) and provided with a gate dielectric liner (54, 92). A poly-SC gate (60′) deposited in the cavity (50) has a central fissure (empty pipe) (63) extending through to the underlying SC (40). This fissure (63) is used to etch the void (70, 100) in the SC (40) beneath the poly-gate (60′). The fissure (63) is then closed by a dielectric plug (74, 84, 102) formed by deposition or oxidation without significantly filling the etched void (70, 100). Conventional process steps are used to provide the source (24) and body regions (25) around the cavity (50) containing the gate (60′), and to provide a drift space (26) and drain region (27) below the body region (25). The etched void (70, 100) between the gate (60′) and drain (27) provides lower Cgd and Ron*Qg than can be achieved using low k dielectrics.