US Patent 7836377 Semiconductor memory device

A semiconductor memory device has a built-in error detection and correction system, wherein the error detection and correction system is formed to have a cyclic code, with which multiple error bits are correctable, and wherein the cyclic code is configured in such a manner that a certain number of degrees are selected as information bits from the entire degree of an information polynomial having degree numbers corresponding to an error-correctable maximal bit number, the certain number being a number of data bits which are simultaneously error-correctable in the memory device.