US Patent 7830221 Coupling cancellation scheme

Methods and apparatus are disclosed, such as those involving an interconnection layout for an integrated circuit (IC). One such layout includes a plurality of differential pairs of lines. Each differential pair has two lines including one or more parallel portions extending substantially parallel to each other. Each pair also includes a shield line. Each of the shield lines includes one or more parallel portions interposed between the parallel portions of one of the pairs of differential lines. One or more of the shield lines are electrically connected to a voltage reference, such as ground. This layout is believed to reduce or eliminate intra-pair coupling as well as inter-pair coupling.