US Patent 7829986 Integrated circuit package system with net spacer

A method for manufacturing an integrated circuit package system is provided including: forming a strip level net spacer including support bars, tie bars and paddles; configuring the support bars, the tie bars and the paddles to form four or more open regions around each of the paddles; and interconnecting the support bars, the tie bars and the paddles to provide structural support to vertically stacked semiconductor devices formed above first semiconductor devices and directly attached to the paddles.