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US Patent 7817673 Clock synchronisation over a packet network

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Edits on 10 Oct, 2024

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Patent Citations Received

US Patent 12113884 Method and apparatus for adapting, at a sink node, a constant bit rate client signal into the path layer of a telecom signal

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Patent Citations Received

US Patent 11916662 System and method for performing rate adaptation of constant bit rate (CBR) client data with a fixed number of idle blocks for transmission over a metro transport network (MTN)

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Edits on 7 Dec, 2023

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Patent Citations Received

US Patent 11838111 System and method for performing rate adaptation of constant bit rate (CBR) client data with a variable number of idle blocks for transmission over a metro transport network (MTN)

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Edits on 31 Oct, 2023

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edited on 31 Oct, 2023

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Article

Patent abstract

A method of synchronising first and second clocks coupled respectively to ingress and egress interfaces 6,7 of a packet network 1, the method comprising calculating a minimum packet Transit Time over the network 1 in each of successive time intervals, and varying the frequency of the second clock so as to track variations in the minimum packet Transit Time.

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Patent Inventor Names

Geoffrey Edward Floyd0

Martin Crowle0

Martin Raymond Scott0

Timothy Michael Edmund Frost0

Edits on 24 May, 2023

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Patent Citations Received

US Patent 11659072 Apparatus for adapting a constant bit rate client signal into the path layer of a telecom signal

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Official Website

https://pdfpiw.uspto.gov/.piw?Docid=07817673

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US Patent 07817673 Clock synchronisation over a packet network US Patent 7817673 Clock synchronisation over a packet network

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Patent Number

07817673

Patent Number

7817673

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edited on 3 Jun, 2022

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Website URL

https://pdfpiw.uspto.gov/.piw?Docid=07817673

Edits on 6 Dec, 2021

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US Patent 07817673 Clock synchronisation over a packet network

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Is a

Patent jurisdiction

United States Patent and Trademark Office

Patent number

07817673

Date of patent

October 19, 2010

Patent application number

12056735

Date Filed

March 27, 2008

Patent primary examiner

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