US Patent 7808273 Reducing leakage power in low power mode

Sequential circuitry comprising a data input, a data output, a clock signal input and a clamp signal input is disclosed. The sequential circuitry is arranged to clock a data signal received at said data input into said sequential circuitry in response to a clock signal received at said clock signal input, and to output a data signal from said sequential circuitry at said data output in response to said clock signal. The sequential circuitry is responsive to a predetermined value at said clamp signal input to switch to a low power mode and to set said data output to a forced value, while retaining said sequential state within said circuitry, said forced value being selected to reduce leakage power from combinatorial circuitry arranged to receive said output data signal.