US Patent 7800957 Data output circuit in semiconductor memory apparatus

A data output circuit in a semiconductor memory apparatus includes a first data driving unit configured to generate a first driving data at a first timing, a first buffering unit configured to generate a first output data by buffering the first driving data, a second data driving unit configured to generate a second driving data at a second timing that is different from the first timing, and a second buffering unit configured to generate a second output data by buffering the second driving data.