Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Riccardo Badalone0
Claus Reitlingshoefer0
Dirk Pfaff0
Date of Patent
September 14, 2010
0Patent Application Number
117907070
Date Filed
April 27, 2007
0Patent Primary Examiner
Patent abstract
Where high speed communication between a host and memory devices is carried over serial bit lanes, memory buffers are required for converting buffering the serial bit lanes, and for converting between serial and parallel formats. In addition, jitter, wander, and skew between the bit lanes need to be accommodated. The invention discloses a programmable asynchronous FIFO with the integrated ability to convert blocks of bits from serial to parallel as well as inserting bits from a parallel bus into the serial bit stream. The invention provides very low latency and can be implemented in low power technologies.
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