Patent attributes
An iterative decoder includes at respective variable nodes, that is, at nodes that correspond to the bits of the code word, bit error detectors that after convergence determine if the respective hard decision bit values have changed from the bit values provided by the channel. The change in value for a given bit indicates that a bit error has been corrected. The bit error detector, for message-passing decoders that perform calculations by addition rather than multiplication, can be readily implemented as an XOR gate. Thus, a bit error is detected at the variable node by XOR'ing the sign bits of the input symbol and the variable node sum. After convergence, the output values produced by the bit error detectors at the respective variable nodes are added together using an adder tree that accumulates the detected bit errors for an entire date block, or ECC code word. Alternatively, the system may group the bits into respective code word symbols and combine the bit error values into symbols-with-errors values using, for example, XOR sub-trees that produce, for each symbol, a single error value. The error value for a given symbol indicates that the symbol is either error-free or includes one or more bit errors, and a total count of the symbols with errors is produced by adding the error values together.
