US Patent 7793190 Reduced clash GRA interleavers

Methods, apparatuses, and systems are presented for performing data encoding involving receiving a sequence of data bits, encoding the sequence of data bit according to a code characterized by a parity check matrix (H matrix) to generate a sequence of encoded bits, wherein the H matrix is capable of being expressed as H=[Hp|Hd]=[S|J*P*T], S being a dual-diagonal matrix, J being a single parity check matrix, P being an interleaver permutation matrix, and T being a repeat block matrix, wherein the H matrix is a column permuted version of an original H matrix, wherein clashes associated with an interleaver corresponding to the P matrix are reduced by adopting the H matrix instead of the original H matrix, and outputting the sequence of encoded bits.