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US Patent 7793129 Power consumption decrease memory management method

Patent 7793129 was granted and assigned to Hitachi on September, 2010 by the United States Patent and Trademark Office.

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Patent

Patent attributes

Current Assignee
Hitachi
Hitachi
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
7793129
Date of Patent
September 7, 2010
Patent Application Number
11729957
Date Filed
March 30, 2007
Patent Primary Examiner
‌
Suresh K Suryawanshi
Patent abstract

The power consumed by a memory is reduced without affecting the performance whereby a processor accesses the memory. A state of a power supplied to the memory is controlled to one of an active state wherein a storage area included in the memory rank can be accessed from the processor, and an inactive state wherein access cannot be performed without a delay for each memory rank, the basic system software prevents fragmentation in which the allocated storage area spans a plurality of memory ranks, puts the power state of a memory rank which does not include an allocated storage area into the inactive state, and puts the power state of a memory rank which includes a storage area required for allocation first into the active state.

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