US Patent 7793082 Latch to block short path violation

An integrated circuit includes processing pipeline stages formed of an input register, processing circuit and an output register. The output register employs speculative sampling and uses a subsequent speculation period during which any change in its input is detected and used to indicate a speculation error. In order to reduce the chances of a race condition giving rise to a false positive detection of a speculation error due to a too rapid signal propagation through the processing circuitry a transparent latch is disposed at the approximate midpoint, measured in terms of propagation delay, within the processing circuitry. This transparent latch is non-transmissive during the speculation period of the output register so as to prevent any new signal propagating from the input register during the speculation period from reaching the output register.