Patent attributes
A method and apparatus generates a clock frequency dependent on a reference clock signal and has a phase locked loop configuration. A multiplexer is connected into the transmission path of the respective incoming input signal, to which the corresponding input signal is fed directly, on the one hand, and in delayed fashion, on the other hand. The common clock signal used is a system clock signal, independent of the reference clock signal and the local clock signal and whose frequency is higher by a factor of at least “5” than the frequency of the reference clock signal and of the local clock signal, respectively. The temporal spacing between the edges of the undelayed clock signal, and of the delayed clock signal, is set such that it is greater than the temporal spacing of the sampling pulses of the phase detector that are predetermined by the system clock signal.
