US Patent 7769955 Multiple thread instruction fetch from different cache levels
Patent 7769955 was granted and assigned to Arm on August, 2010 by the United States Patent and Trademark Office.
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A data processing apparatus is provided wherein processing circuitry executes multiple program threads including at least one high priority thread and at least one lower priority thread. Instructions required by the threads are retrieved from a cache memory hierarchy comprising multiple cache levels. The cache memory hierarchy includes a bypass path for omitting a predetermined level of the cache memory hierarchy when performing a lookup procedure for a required instruction and for bypassing said predetermined level of the cache memory hierarchy when returning said required instruction to said processing circuitry. The bypass path is used by default when the requested instruction is for a lower priority thread.
US Patent 07769955 Multiple thread instruction fetch from different cache levels US Patent 7769955 Multiple thread instruction fetch from different cache levels
US Patent 07769955 Multiple thread instruction fetch from different cache levels
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