Patent attributes
A circuit, method, and computer readable medium for on-chip measuring of noise margins in a memory device memory device are disclosed. The on-chip method includes electrically coupling at least a first circuit to a memory cell. A voltage divider is electrically coupled to at least a first voltage and a second voltage. A multiplexer circuit is electrically coupled to the voltage divider. The multiplexer selects one of the first voltage and second voltage for producing a test voltage. A selecting line is electrically coupled to a force\measure network. A comparator is coupled to the force\measure network. The force-measure network supplies the test voltage to the comparator and a measured voltage to the comparator for determining when the measured voltage exceeds the test voltage.
