US Patent 7768134 Interconnect structure and method for semiconductor device
Patent 7768134 was granted and assigned to Toshiba America Electronic Components on August, 2010 by the United States Patent and Trademark Office.
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An interconnect method in a semiconductor device may include a step of examining various regions of an inter layer dielectric to identify regions having high densities or concentrations of trench features. A cap insulator layer may be added to the dielectric to assist in outgassing of absorbed impurities from the dielectric, but may be removed from the high density areas to allow the lower density areas to increase outgassing. The lower density areas may then compensate for increased outgassing on the high density areas due to the trench features, and may result in an overall device with a more stable dielectric constant across the device.
US Patent 07768134 Interconnect structure and method for semiconductor device US Patent 7768134 Interconnect structure and method for semiconductor device
US Patent 07768134 Interconnect structure and method for semiconductor device
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