Patent attributes
System and method for creating a time alignment analog notch. An embodiment includes a digital power amplifier coupled to an enable signal line and to a digital control bits bus, and a matching network coupled to the digital power amplifier. The matching network to provide impedance matching and the digital power amplifier to produce a current based on a value on the digital control bits bus. The digital power amplifier comprises a selection circuit and a plurality of transistors. The transistors, controlled by outputs of the selection circuit, provide a current based on the value on the digital control bits bus. The adjustment of a delay between a signal on the enable signal line and the values on the digital control bits bus creates an analog notch at about Fs/2, where Fs is a sampling frequency of a sigma-delta modulator used to modulate data provided to the digital power amplifier.
