US Patent 7760568 Memory sensing and latching circuit

According to one exemplary embodiment, a memory sensing and latching circuit includes a sensing circuit for evaluating bit lines in a memory array and providing a sensed output. The memory sensing and latching circuit further includes a latching circuit including a dynamic one-shot circuit driven by the sensed output, a sense amplifier enable signal, and a precharge clock. The latching circuit further includes a storage circuit for storing a one-shot output of the dynamic one-shot circuit, where the one-shot output corresponds to the sensed output. The one-shot output of the dynamic one-shot circuit is stored in the storage circuit during an evaluation of the sensed output. The evaluation of the sensed output is responsive to the sense amplifier enable signal.