US Patent 7754551 Method for making very low

Patent 7754551 was granted and assigned to National Chiao Tung University on July, 2010 by the United States Patent and Trademark Office.

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Is a

Patent

Patent attributes

Current Assignee

National Chiao Tung University

Patent Jurisdiction

United States Patent and Trademark Office

Patent Number

7754551

Date of Patent

July 13, 2010

Patent Application Number

12216561

Date Filed

July 8, 2008

Patent Primary Examiner

‌

Alexander G Ghyka

Patent abstract

This invention proposes a method for making very low threshold voltage (Vt) metal-gate/high-κ CMOSFETs using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with VLSI. At 1.2 nm equivalent-oxide thickness (EOT), good effective work-function of 5.3 and 4.1 eV, low Vt of +0.05 and 0.03 V, high mobility of 90 and 243 cm2/Vs, and small 85° C. bias-temperature-instability <32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.