Patent attributes
One embodiment of the present invention provides a system that executes a transaction on a multi-threaded processor. The system starts by executing the transaction in a “transaction-pending mode,” which involves placing load-marks or store-marks on cache lines loaded from or stored to during transaction-pending mode and also buffers store operations in a store queue. Upon encountering a store queue overflow, the system continues to execute the transaction in a “store-queue-overflow mode,” which involves placing load-marks or store-marks on cache lines loaded from or stored to during store-queue-overflow mode and discards store data which does not fit into the store queue during store operations. Upon completing the transaction in the store-queue-overflow mode, the system re-executes the transaction in a “repeating-transaction mode,” which involves executing the instructions in the transaction non-speculatively, which allows the store operations to commit to the memory hierarchy.
