US Patent 7729176 Program acceleration of a memory device

Selective program acceleration of a memory device is generally described. A method includes applying a first bias voltage to one or more bit lines coupled with a plurality of cells to be programmed, applying one or more program pulses to the plurality of cells, verifying the plurality of cells at a target threshold voltage to determine whether one or more cells of the plurality of cells have reached or surpassed the target threshold voltage, identifying slower cells of the plurality of cells, and selectively accelerating a program speed of the slower cells to reduce a programming time of a memory device.