US Patent 7723714 Programmable-resistance memory cell

A memory cell (10) comprising at least a source electrode (MS) formed on a substrate (6); at least a drain electrode (MD) formed on the substrate (6); at least a coupling layer (1) formed between the source electrode (MS) and the drain electrode (MD), and at least a gate electrode (MG) formed on the substrate (6), wherein the coupling layer (1) comprises a transition-metal oxide exhibiting a filling-controlled metal-insulator transition property; the gate electrode (MG) comprises an oxygen ion conductor layer (2), and the gate electrode (MG) is arranged relative to the coupling layer (1) such that application of an electrical signal to the gate electrode (MG) causes alteration of the oxygen vacancy (3) concentration in the coupling layer (1).