Is a
Patent attributes
Current Assignee
0
Patent Jurisdiction
Patent Number
Patent Inventor Names
Shiao-Shien Chen0
Date of Patent
May 18, 2010
0Patent Application Number
111634660
Date Filed
October 20, 2005
0Patent Primary Examiner
Patent abstract
An ESD protection design using a gate-coupled substrate-triggered technique is provided. A required RC time constant maintained in the gate-coupled substrate-triggered ESD circuit is based on a parasitic MOS capacitor and larger resistor, in which a layout area for the substrate-triggered ESD protection design is significantly reduced.
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