Patent attributes
A high-power solid-state transistor structure comprised of a plurality of emitter or gate fingers arranged in a uniform or non-uniform manner to provide improved high power performance is disclosed. Each of the fingers is associated with a corresponding one of a plurality of sub-cells. In an exemplary embodiment, the fingers may be arranged in a 1-D or 2-D form having a “hollow-center” layout where one or more elongated emitter fingers or subcells are left out during design or disconnected during manufacture. In another exemplary embodiment, the fingers may be arranged in a 1-D or 2-D form having one or more “arc-shaped” rows that includes one or more elongated emitter fingers or subcells. The structure can be practically implemented and the absolute thermal stability can be maintained for very high power transistors with reduced adverse effects due to random variation in the manufacturing and design process.
