Patent attributes
An analogue multiplier circuit has an input coefficient voltage dependent adjustment of its frequency response. The multiplier contains a multiplier cell (MC) with an RF input (Vin+, Vin−) and a coefficient signal input (Vcoeff+, Vcoeff−), one or more capacitors (Cp1, Cp2) as peaking capacitors, which one contact connects to the multiplier cell (MC) and the other to a variable resistance (Mp1, Mp2), i.e. a MOS transistor, and a control circuit (CT) for controlling the variable resistance (Mp1, Mp2). The control circuit (CT) is connected to the coefficient signal input (Vcoeff+, Vcoeff−) of the multiplier. In the case of a four-quadrant multiplier a rectifier (RT) is connected between the coefficient input (Vcoeff+, Vcoeff−) of the multiplier and the control circuit (CT).
