US Patent 7697333 NAND flash memory

A NAND flash memory including a memory cell array having a plurality of blocks, each of the blocks is composed of a plurality of memory cell units, drain-side select gate transistors, and source-side select gate transistors. The NAND flash memory further includes a row decoder that is connected to word lines, the drain-side select gate lines, and the source-side gate line of the memory cell array, and that applies a signal voltage to word lines, the drain-side select gate lines and the source-side gate line of the memory cell array for selecting blocks. The NAND flash memory further includes a sense amplifier that is controlled by a column decoder and that makes a selection from the bit lines of the memory cell array.